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programmable low voltage 1:10 lvds clock driver ADN4670 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features low output skew <30 ps (typical) distributes one differential clock input to 10 lvds clock outputs programmableone of two differential clock inputs can be selected (clk0, clk1) and individual differential clock outputs enabled/disabled signaling rate up to 1.1 ghz (typical) 2.375 v to 2.625 v power supply range 100 mv differential input threshold input common-mode range from rail-to-rail i/o pins fail-safe during power-down: v dd = 0 v available in 32-lead lfcsp package industrial operating temperature range: ?40c to +85c applications clock distribution networks functional block diagram 9876543210 10 12-bit counter 11-bit shift register 11-bit control register q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 ck si en clk0 clk1 mux mux 1 0 clk0 clk1 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 0 1 08870-001 figure 1. general description the ADN4670 is a low voltage differential signaling (lvds) clock driver that expands a differential clock input signal to 10 differential clock outputs. the device is programmable using a simple serial interface, so that one of two clock inputs can be selected (clk0/ clk0 or clk1/ clk1 ) and any of the differential outputs (q0/ q0 to q9/ q9 ) can be enabled or disabled (tristated). the ADN4670 is designed for use in 50 transmission line environments. when the enable input en is high, the device may be pro- grammed by clocking 11 data bits into the shift register. the first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), while the 11 th bit selects the clock input (0 = clk0, 1 = clk1). a 12 th clock pulse transfers data from the shift register to the control register. the ADN4670 is fully specified over the industrial temperature range and is available in a 32-lead lfcsp package.
ADN4670 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 jitter characteristics ..................................................................... 3 lvds switching characteristics ................................................. 4 programming logic ac characteristics ................................... 5 absolute maximum ratings ............................................................6 esd caution...................................................................................6 pin configuration and function descriptions ..............................7 theory of operation .........................................................................8 lvds reciever input termination .............................................8 fail-safe operation .......................................................................8 programming .................................................................................8 outline dimensions ..........................................................................9 ordering guide .............................................................................9 revision history 4/10revison 0: initial version
ADN4670 rev. 0 | page 3 of 12 specifications v dd = 2.375 v to 2.625 v; all specifications t min to t max , unless otherwise noted. table 1. parameter symbol min typ max unit conditions/comments receiver input high threshold at clk0/ clk0 or clk1/ clk1 v th 100 mv input low threshold at clk0/ clk0 or clk1/ clk1 v tl ?100 mv differential input voltage |v id | 200 mv input common-mode voltage v ic 0.5|v id | v dd ? 0.5|v id | input current at clk0, clk0 , clk1, or clk1 i ih , i il ?5 +5 a v i = v dd or v i = 0 v input capacitance c i 3 pf v i = v dd or gnd driver differential output voltage |v od | 250 450 600 mv r l = 100 v od magnitude change v od 50 mv offset voltage v os 0.95 1.2 1.45 v ?40c to +85c v os magnitude change v os 350 mv output short circuit current i os ?20 ma v o = 0 v 20 ma |v od | = 0 v reference output voltage v bb 1.15 1.25 1.35 v v dd = 2.5 v, i = ?100 a output capacitance c o 3 pf v o = v dd or gnd supply current supply current i dd 35 ma all outputs tristated, f = 0 hz 100 110 ma all outputs enabled and loaded, r l = 100 , f = 100 mhz 150 160 ma all outputs enabled and loaded, r l = 100 , f = 800 mhz jitter characteristics table 2. parameter symbol min typ max unit conditions/comments additive phase jitter from inp ut to lvds outputs, q3 and q3 t jitter lvds 281 f s rms 12 khz to 5 mhz, f out = 30.72 mhz 111 f s rms 12 khz to 20 mhz, f out = 125 mhz
ADN4670 rev. 0 | page 4 of 12 lvds switching characteristics v dd = 2.375 v to 2.625 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max 1 unit conditions/comments propagation delay low to high t plhx 2 3 ns from clk0/ clk0 or clk1/ clk1 to any qx/ qx propagation delay high to low t phlx 2 3 ns from clk0/ clk0 or clk1/ clk1 to any qx/ qx duty cycle t duty 45 55 % from clk0/ clk0 or clk1/ clk1 to any qx/ qx output skew 2 t sk(o) 30 ps any qx/ qx pulse skew 3 t sk(p) 50 ps any qx/ qx part-to-part output skew 4 t sk(pp) 600 ps any qx/ qx output rise time t r 350 ps any qx/ qx , 20% to 80%, r l = 100 c l = 5 pf output fall time t f 350 any qx/ qx , 80% to 20%, r l = 100 c l = 5 pf maximum input frequency f clk 900 1100 mhz from clk0/ clk0 or clk1/ clk1 to any qx/ qx 1 guaranteed by design and characterization. 2 output skew is defined as the difference between the largest and smallest values of t plhx within a device or the difference between the largest and smallest values of t phlx within a device, whichever of the two is greater. 3 pulse skew is defined as the magnitude of the maximum difference between t plh and t phl for any channel of a device, that is, |t phlx C t hlpx |. 4 part-to-part output skew is defined as the difference between the largest and smallest values of t plhx across multiple devices or the difference between the largest and smallest values of t phlx across multiple devices, whichever of the two is greater. t plh0 t plh1 t plh9 t phl0 t phl1 t phl9 c lk c lk q0 q0 q1 q1 q9 q9 08870-002 figure 2. waveforms for calculation of t sk(o) and t sk(pp)
ADN4670 rev. 0 | page 5 of 12 250mv 250mv 80% 20% 5% 5% t/2 t/2 differential output signal v od = (qx) ? (qx) 0v differential 08870-003 figure 3. test criteria for f clk , t r , t f , and v od programming logic ac characteristics v dd = 2.375 v to 2.625 v; all specifications t min to t max , unless otherwise noted. table 4. parameter symbol min typ max unit conditions/comments maximum frequency at ck input f max 100 150 mhz setup time, si to ck t su 2 ns time for which si must not change before the ck 0-to-1 transition hold time, ck to si t h 1.5 ns time for which si must not change after the ck 0-to-1 transition en to ck removal time t removal 1.5 ns removal time, en to ck start-up time t startup 1 s start-up time after disable through si minimum clock pulse width t w 3 ns logic input high level v ih 2 v v dd = 2.5 v logic input low level v il 0.8 v v dd = 2.5 v high level logic input current, ck i ih ?5 +5 a v i = v dd high level logic input current, si and en +10 ?30 a v i = v dd low level logic input current, ck i il ?10 +30 a v i = gnd low level logic input current, si and en ?5 +5 a v i = gnd
ADN4670 rev. 0 | page 6 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v cc to gnd ?0.3 v to +2.8 v input voltage to gnd ?0.2 v to ( v dd + 0.2) v output voltage to gnd ?0.2 v to ( v dd + 0.2) v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja lfcsp package ja thermal impedance 32.5c/w reflow soldering peak temperature pb-free 260c 5c esd (human body model, 1.5 k 100 pf) 4000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADN4670 rev. 0 | page 7 of 12 3 6 notes 1. the exposed pad can be connected to ground or left floating. v v pin configuration and fu nction descriptions 1q 2 q3 3 q4 4 q4 5 q5 6 q5 7 q6 8q 24 23 22 21 20 19 18 17 ck si clk0 clk0 v bb clk1 clk1 en 9 10 11 12 13 14 15 16 ss q9 q9 q8 q8 q7 q7 dd 32 31 30 29 28 27 26 25 v dd q0 q0 q1 q1 q2 q2 v ss top view (not to scale) ADN4670 088 70-004 figure 4. pin configuration table 4. pin function descriptions pin o. mneonic description 1 ck programming clock. programming data is clocked in on a low-to-high transition at this input. if left open-circuit, it is pulled high by a 120 k resistor. 2 si serial data input. this is the inp ut for programming data. if left open-ci rcuit, it is pulled low by a 120 k resistor. 3 clk0 noninverting differential clock input 0. 4 clk0 inverting differential clock input 0. 5 v bb reference voltage output. 6 clk1 noninverting differential clock input 1. 7 clk1 inverting differential clock input 1. 8 en active-high enable input. when this input is high, programming is enab led. if left open-circuit, it is pulled low by a 120 k resistor. 9, 25 v ss device ground. 10, 12, 14, 17, 19, 21, 23, 26, 28, 30 q9 to q0 inverted clock output. when the different ial input voltage is between clkx and clkx > 100 mv, this output sinks current. when the different ial input voltage is between clkx and clkx < ?100 mv, this output sources current. 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 q9 to q0 noninverted clock output. when the differe ntial input voltage is between clkx and clkx > 100 mv, this output sources current. when the differential input voltage is between clkx and clkx < ?100 mv, this output sinks current. 16, 32 v dd power supply input. this part can be operated from 2.375 v to 2.625 v.
ADN4670 rev. 0 | page 8 of 12 theory of operation the ADN4670 is a clock driver/expander for low voltage diffe- rential signaling (lvds). it takes a differential clock signal of typically 350 mv and expands it to 10 differential clock outputs with very low skew (typically < 30 ps). the device receives a differential current signal from a source such as a twisted pair cable, which develops a voltage of typically 350 mv across a 100 terminating resistor. this signal passes via a differential multiplexer to 10 drivers that each output a differential current signal. the device is programmable using a simple serial interface. one of two differential clock inputs (clk0/ clk0 or clk1/ clk1 ), can be selected and any of the differential outputs (q0/ q0 to q9/ q9 ) can be enabled or disabled. lvds reciever input termination terminate the clock inputs with 100 resistors from clk0 to clk0 and clk1 to / clk1 , placed as close as possible to the input pins. fail-safe operation in power-down mode (v dd = 0 v), the ADN4670 has fail-safe input and output pins. in power-on mode, fail-safe biasing can be achieved by connecting 10 k pull-up resistors from clk0 and clk1 to v dd and 10 k pull-down resistors from clk0 and clk1 to gnd. programming three control inputs are provided for programming the ADN4670. en is the enable input, which allows programming when high, si is the serial data input, and ck is the serial clock input, which clocks data into the device on a low-to-high clock transition. each of these inputs has an internal pull-up or pull-down resistor of 120 k. en and si are pulled low if left open-circuit while ck is pulled high. the default condition if these inputs are left open-circuit is that all outputs are enabled, and the state of si selects the inputs (0 = clk0/ clk0 , 1 = clk1/ clk1 ). this is the standard operating mode for which no programming of the device is required. programming is enabled by taking en high. the data on si is then clocked into the device on each 0-to-1 transition of ck. data on si must be stable for the setup time (t su ) before the clock transition and remain stable for the hold time (t h ) after the clock transition. to program the device, 11 bits of data are needed, starting with bit 0, which enables or disables outputs q9/ q9 , through to bit 10, which selects either clk0/ clk0 or clk1/ clk1 as the inputs. a 12 th clock pulse is then required to transfer data from the shift register to the control register. a low-to-high transition on en resets the control register and the next 12 ck pulses are programmed. table 5. control logic truth table ck en si clk0 clk0 clk1 clk1 q0 to q9 q0 to q9 l l l l h x x l h l l l h l x x h l l l l open open x x l h l l h x x l h l h l l h x x h l h l l l h x x open open l h table 6. state machine inputs en si ck output l l x default state with all outp uts enabled, clk0 selected, and the control register disabled l h x all outputs enabled, clk1 selected, and the control register disabled h l first stage stores low, other stag e stores data of previous stage h h first stage stores high, other stag e stores data of previous stage l x x reset the state machine, control register, and shift register table 7. serial input sequence bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clk_sel q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 table 8. control register bit 10 bit[9:0] qx[9:0] l h clk0 h h clk1 x l outputs disabled
ADN4670 rev. 0 | page 9 of 12 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.25 3.10 sq 2.95 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 5. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADN4670bcpz ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 ADN4670bcpz-reel7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 1 z = rohs compliant part.
ADN4670 rev. 0 | page 10 of 12 notes
ADN4670 rev. 0 | page 11 of 12 notes
ADN4670 rev. 0 | page 12 of 12 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08870-0-4/10(0)

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